1. Field of the Invention
The present invention relates to a memory cell array which is capable of increasing the quantity of stored charges of memory cells provided in a memory cell array of a DRAM (dynamic random access memory) by means of a simple configuration to thereby improve the operating margin of the memory cell array, and to a method of controlling such a memory cell array.
Priority is claimed on Japanese Patent Application No. 2007-163639, filed Jun. 21, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
There are known technologies to drive common electrodes (plate electrodes) of capacitors of memory cells provided in a memory cell array of a DRAM using pulses (i.e., a plate-driving scheme) to thereby substantially increase the quantity of stored charges (for example, see Patent Literatures 1 and 2, and non-Patent Literatures 1, 2, and 3).
Patent Literature 1: Japanese Unexamined Patent Application, First Publication No. S58-48294
Patent Literature 2: Japanese Unexamined Patent Application First Publication No. H 11-260054
Non-Patent Literature 1: K. Fujishima et al., “A Storage-Node-Boosted RAM with Word-Line Delay Compensation”, IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 5, October 1982
Non-Patent Literature 2: M. Aoki et al., “A 1.5-V DRAM for Battery-Based Applications”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989
Non-Patent Literature 3: T. Yamauchi et al., “High-Performance Embedded SOI DRAM Architecture for the Low-Power Supply”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 8, August 2000
In general, the use of the plate-driving scheme (which will be hereinafter simply referred to as “plate-drive”) makes it possible to increase either one of the quantity of stored charges of a logic High (“H”) signal and the quantity of stored charges of a logic Low (“L”) signal. It is to be noted that, in the following description, the logic High (“H”) will be simply referred to as “High”, and the logic Low (“L”) will be simply referred to as “Low” as the occasion may demand.
In related arts, a differential-input sense amplifier is used to sense the quantity of the stored charges which have been read out on a bit line and to amplify the quantity of stored charges, and thus a reference voltage is required for determining whether data which has been read out is a High data or a Low data.
Ordinarily, a reference voltage is set to the substantially middle voltage between the voltage of a bit line when a high level signal is read out thereon and the voltage of a bit line when a low level signal is read out thereon, thus ensuring the same sensing margins regardless of which data is read out. When the plate-drive is not performed, it is sufficient to use the middle voltage between the voltage of a high level signal on a bit line and the voltage of a low level signal on a bit line as a reference voltage. For example, such a reference voltage can be relatively easily generated by short-circuiting a bit line which has been amplified so as to be a high level and a bit line which has been amplified so as to be a low level.
However, when the plate-drive is performed, either the quantity of the stored charges of a high level signal or the quantity of the stored charges of a low level signal is increased. As a result, the reference voltage greatly shifts from the middle voltage. For this reason, in the related arts, dummy cells are added to generate a reference voltage.
For instance, in the related arts shown in FIG. 7 (FIG. 3 of the Patent Literature 1) and FIG. 8 (FIG. 3 of the non-Patent Literature 3), the quantity of stored charges corresponding to a Low data is increased by a plate-drive, and thus a reference voltage of a differential-input sense amplifier is adjusted by using a dummy cell such that the reference voltage is equal to a voltage which is substantially one half of the voltage when a High data is read out and the voltage when a Low data is read out.
However, there is the problem in that when dummy cells are used, current consumption for driving the dummy cells would be increased. Moreover, there is the problem in that the chip area is increased because dummy cells are disposed. Furthermore, there is the problem in that when the dummy cells become defective, the yield would be reduced because it is impossible to perform a remedy using a redundancy configuration.